Electrostatic discharge protection device and method of fabricating the same

ABSTRACT

An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method offabricating the same. More specifically, the present invention relatesto an electrostatic discharge protection device and a method offabricating the same.

2. Description of the Related Art

An integrated circuit (IC) including a MOS field effect transistor(MOSFET) may be easily damaged by an electrostatic discharge (ESD). AnESD may be delivered to an IC from an input/output (I/O) pin, a powerpin, or a pad of another IC, and may attack a junction of a transistor,a dielectric and a unit device.

Various structures of an ESD protection circuit have been developed toprotect devices from an ESD. An important role of an ESD protectioncircuit is to guide the ESD current from an easily attackable circuit toa low-impedance path.

Such an ESD protection circuit may be connected between an I/O and powerpins and an internal circuit in parallel, and functions to guide the ESDcurrent to an external region by providing a current path at a low powerduring an ESD. A representative discharge protection circuit may becategorized into a silicon controlled rectifier (SCR) and an npn bipolartransistor. An SCR instantly discharges an ESD current to a node Vssusing a parasitic npnp diode. An npn bipolar transistor discharges anESD current to a node Vss by an operation of a parasitic npn bipolartransistor of a MOS transistor based on a snap-back phenomenon. Such anESD protection circuit may use a gate grounded NMOS transistor (ggNMOS)for a structure of the npn bipolar transistor.

FIG. 1 is a circuit diagram of a conventional ESD protection circuitusing a ggNMOS transistor. FIG. 2 is a graph illustrating avoltage-current (V-I) characteristic of the ggNMOS transistor of FIG. 1when an electrostatic current is discharged.

Referring to FIG. 1, an ESD protection circuit 5 is connected inparallel between a pad 1 and an internal circuit 3. A drain of theggNMOS transistor is electrically connected to a pad 1. A gate, a sourceand a channel of the transistor are connected to a ground node Vss.

Referring to FIG. 2, when a voltage higher than a trigger voltage Vt isapplied to the ggNMOS transistor by an ESD, a break down of the drainjunction in the ggNMOS transistor causes a portion of charges to flow ina substrate. The charges make the parasitic npn transistor turned-on todischarge a large amount of ESD current through a low-impedance path tothe Vss node instantly. Therefore, the internal circuit 3 is protectedfrom damage.

Three issues may degrade the robustness of an ESD protection device.These issues are an increase of a surface current density during an ESD,a hot-carrier issue and Joule heating. In an effort to solve thisproblem, a silicide blocking layer may be formed between the gate andthe source/drain contact of the ggNMOS. However, such a structurerequires that the silicide be separated at an area where thesource/drain contact is connected to a gate. Further, such a structurehas a disadvantage of increasing an area of the ESD circuit.

FIG. 3 illustrates another conventional semiconductor device for an ESDprotection device having an n+ drain surrounded by an n-diffusion layerwithout increasing a layout area.

Referring to FIG. 3, the ESD protection device is formed at a p-well 12of a substrate 10 and includes NMOS transistors T₁ and T₂ connected inseries sharing an n+ drain 20. Each NMOS transistor T₁ and T₂ includes agate electrode 14. Sources 16 of each of the NMOS transistors T₁ and T₂and a p+ guard ring 18 are connected to a node Vss. The n+ drain 20 iselectrically connected to a pad 24. The device includes an n-diffusionlayer 22 surrounding the n+ drain 20 to overcome an increase of surfacecurrent density and a hot carrier issue. The n− diffusion layer 22includes a space under the n+ drain 20.

The space under the n+ drain 20 has a relatively low breakdown voltage.Therefore, the substrate current is generated through the space when anESD voltage is applied to the n+ drain 20 and discharged throughparasitic npn bipolar transistors Q₁ and Q₂ in the NMOS transistor tothe node Vss. This structure may improve ESD robustness because acurrent path is separated from a substrate surface and a transistorchannel that are relatively weak. However, such a structure is formedthrough a complicated process because it requires an additional layerfor forming the n-diffusion layer 22 having the space under the n+ drain20.

SUMMARY OF THE INVENTION

The present invention is therefore directed to an electrostaticdischarge protection device and a method of fabricating the same, whichsubstantially overcome one or more of the problems due to thelimitations and disadvantages of the related art.

It is a feature of an embodiment of the present invention to provide anESD protection device, and a method of forming the same, having good ESDrobustness.

It is another feature of an embodiment of the present invention toprovide an ESD protection device, and a method of forming the same, thathas increased robustness without increasing an area of the ESD circuit.

It is still another feature of an embodiment of the present invention toprovide an ESD protection device, and a method of forming the same, thatis capable of being fabricated without requiring additional complicatedprocesses.

At least one of the above and other features and advantages of thepresent invention may be realized by providing an electrostaticdischarge protection device including a substrate, an n-well formed inthe substrate, a p-well formed on the n-well, an NMOS transistor formedon the p-well, the NMOS transistor including a gate electrode, an n+source and an n+ drain, and a grounded p+ well pick-up formed in thep-well, wherein the n-well is connected to the n+ drain of the NMOStransistor and the n+ source is grounded.

The gate electrode may be grounded. The gate electrode may beelectrically connected to the n+ drain.

An impurity concentration of the n+ drain may be higher than that of then+ source. The n-well may extend vertically under the n+ drain and maycontact the n+ drain. The n-well may extend vertically to form ajunction with the p-well and a junction of the n-well and the p-well mayoverlap the n+ drain.

At least one of the above and other features and advantages of thepresent invention may be realized by providing an electrostaticdischarge protection device including a p-well region formed in asubstrate, an NMOS transistor formed on the p-well region, the NMOStransistor including a gate electrode and an n+ source that areelectrically connected to a ground terminal and an n+ drain electricallyconnected to a circuit terminal, a p+ well pick-up formed in the p-wellregion, electrically connected to the ground terminal, and an n-wellformed under the p-well region, wherein the n-well extends vertically tocontact the n+ drain of the NMOS transistor.

The electrostatic discharge protection device may further include aninterconnection connected to the ground terminal, wherein the n+ source,the gate electrode and the p+ well pick-up may be connected to theinterconnection in parallel.

At least one of the above and other features and advantages of thepresent invention may be realized by providing an electrostaticdischarge protection device connected to a circuit terminal and a groundterminal including a p-well region formed in a substrate, an NMOStransistor formed on the p-well region, the NMOS transistor including agate electrode electrically connected to the circuit terminal, an n+source electrically connected to the ground terminal and an n+ drainelectrically connected to the circuit terminal, a p+ well pick-up formedin the p-well region to be electrically connected to the groundterminal, and an n-well formed under the p-well region, wherein then-well extends vertically to contact the n+ drain of the NMOStransistor.

The electrostatic discharge protection device may further include afirst interconnection connected to the ground terminal, wherein the n+source and the p+ well pick-up are connected to the firstinterconnection in parallel. The electrostatic discharge protectiondevice may further include a second interconnection for connecting thecircuit terminal and the n+ drain, wherein the gate electrode is anextended portion of the second interconnection.

At least one of the above and other features and advantages of thepresent invention may be realized by providing a method of fabricatingthe electrostatic discharge protection device including forming a p-wellregion at an upper portion of a substrate and an n-well region under thep-well region, wherein the n-well region extends vertically along asidewall of the p-well region to define a junction between the p-wellregion and the n-well region at a surface of the substrate, forming ann+ source and an n+ drain separated from each other by implantingimpurities in the p-well region, wherein the n+ drain is formed tooverlap the junction of the p-well region and the n-well region, forminga p+ well pick-up by implanting impurities in the p-well region, andforming an interconnection connected to each of the p+ well pick-up, then+ source and the n+ drain, wherein the p+ well pick-up and the n+source are connected to a ground terminal, and the n+ drain is connectedto a circuit terminal.

The method may further include forming a device isolation layer in thesubstrate to define an active region, before forming the n-well regionand the p-well region, wherein the active region includes the n-wellregion and the p-well region, and the n+ source, the p+ well pick-up andthe n+ drain are formed in the active region.

The method may further include forming a device isolation layer in thesubstrate to define an active region, after forming the n-well regionand the p-well region, wherein the active region includes the n-wellregion and the p-well region, and the n+ source, the p+ well pick up andthe n+ drain are formed in the active region.

An interconnection connected to the n+ drain may extend over a regionbetween the n+ source and the n+ drain, such that an edge of theinterconnection overlaps the n+ source.

At least one of the above and other features and advantages of thepresent invention may be realized by providing a method of fabricatingan electrostatic discharge protection device connected to a circuitterminal and a ground terminal including forming a p-well region at anupper portion of a substrate and an n-well region under the p-wellregion, wherein the n-well region extends vertically along a sidewall ofthe p-well region to define a junction of the p-well region and then-well region at a surface of the substrate, forming a gate electrode onthe p-well region, implanting impurities in the substrate at either sideof the gate electrode to form an n+ source and an n+ drain, wherein then+ drain is formed to overlap a junction between the p-well region andthe n-well region, implanting impurities in the p-well region to form ap+ well pick-up, and forming an interconnection connecting each of thep+ well pick-up, the gate electrode, the n+ source and the n+ drain,wherein the p+ well pick-up and the n+ source are connected to theground terminal, and the n+ drain is connected to the circuit terminal.

The method may further include forming a device isolation layer in thesubstrate to define an active region, before forming the n-well regionand the p-well region, wherein the active region includes the n-wellregion and the p-well region, the gate electrode crosses over the p-wellregion in the active region, and wherein the active region at one sideof the gate electrode includes the p-well region and the active regionat the other side of the gate electrode includes the p-well region andthe n-well region.

The method may further include forming a device isolation layer in thesubstrate to define an active region, after forming the n-well regionand the p-well region, wherein the active region includes the n-wellregion and the p-well region, and wherein the gate electrode crossesover the p-well region in the active region, and the active region atone side of the gate electrode is the p-well region and the activeregion at the other side includes the p-well region and the n-wellregion.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments thereof with reference to theattached drawings in which:

FIG. 1 is a circuit diagram of an ESD protection circuit using a ggNMOStransistor.

FIG. 2 is a graph illustrating a voltage-current (V-I) characteristic ofthe ggNMOS transistor of FIG. 1 when an electrostatic current isdischarged.

FIG. 3 illustrates another conventional semiconductor device for an ESDprotection device.

FIG. 4A illustrates a cross-sectional view of an ESD protection deviceaccording to a first embodiment of the present invention.

FIG. 4B is an equivalent circuit diagram of an ESD protection deviceaccording to the first embodiment of the present invention.

FIG. 5A illustrates a cross-sectional view of an ESD protection deviceaccording to a second embodiment of the present invention.

FIG. 5B is an equivalent circuit diagram of an ESD protection deviceaccording to the second embodiment of the present invention.

FIGS. 6 through 8 illustrate cross-sectional views of stages in a methodof fabricating an ESD protection device according to the firstembodiment of the present invention.

FIGS. 9 through 11 illustrate cross-sectional views of stages in amethod of fabricating an ESD protection device according to the secondembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application 2003-91308, filed on Dec. 15, 2003, in theKorean Intellectual Property Office, and entitled: “ElectrostaticDischarge Protection Device and Method of Fabricating the Same,” isincorporated by reference herein in its entirety.

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. The invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thefigures, the dimensions of films, layers and regions are exaggerated forclarity of illustration. It will also be understood that when a layer isreferred to as being “on” another layer or substrate, it can be directlyon the other layer or substrate, or intervening layers may also bepresent. Further, it will be understood that when a layer is referred toas being “under” another layer, it can be directly under, and one ormore intervening layers may also be present. In addition, it will alsobe understood that when a layer is referred to as being “between” twolayers, it can be the only layer between the two layers, or one or moreintervening layers may also be present. Like reference numerals refer tolike elements throughout.

FIG. 4A illustrates a cross-sectional view of an ESD protection deviceaccording to the first embodiment of the present invention.

Referring to FIG. 4A, the ESD protection device includes an n-well 52formed in a substrate 50 and a p-well 54 formed on the n-well 52. Thep-well 54 extends to a surface of the substrate 50. The n-well 52includes a portion that extends vertically along a sidewall of thep-well 54 to a surface of the substrate 50. A device isolation layer 56is formed in the substrate 50 to define an active region. The activeregion includes a region where the p-well 54 is formed (hereinafter,referred to as a ‘p-well region’) and a region where the n-well 52 isformed (hereinafter, referred to as an ‘n-well region’). A gateelectrode 58 is formed on the active region. The gate electrode 58crosses over the active region and, although not illustrated as doingso, may extend over the device isolation layer 56. The gate electrode 58divides the active region into a first portion of the active at one sideof the gate electrode 58 that includes the p-well region and the n-wellregion and a second portion of the active region to the other side ofthe gate electrode 58 that includes the p-well region. An n+ source 64and an n+ drain 62 are formed in the active regions to either side ofthe gate electrode 58. The gate electrode 58, the n+ source 64 and then+ drain 62 compose an NMOS transistor. The n+ source 64 is formed inthe p-well 54, and the n+ drain 62 is formed to overlap the p-well 54and the n-well 52.

Conventionally, a source and a drain of the NMOS transistor are formedin the p-well or a p-substrate, but the n+ drain 62 of the NMOStransistor in the ESD protection device according to the presentinvention overlaps the p-well 54 and the n-well 52 and contacts then-well 52. An impurity concentration of the n+ drain 62 may be higherthan that of the n+ source 64 due to an influence of the n-well 52.

A p+ well pick-up 66 doped with impurities is formed in the p-wellregion 54. The p+ well pick-up 66 may be separated from the NMOStransistor by the device isolation layer 56. The n+ drain 62 isconnected to a circuit terminal 60 of the integrated circuit. The n+source 64 and the p+ well pick-up 66 are connected to a ground terminal.The circuit terminal 60 may be an input/output (I/O) pin, a data pin ora power pin, and may be electrically connected to an internal circuit.The gate electrode 58 functions to separate the n+ source 64 from the n+drain 62 to form a base of a parasitic npn bipolar transistor. However,the gate electrode 58 may be connected to a ground terminal to preventthe NMOS transistor from operating abnormally due to a voltage drop ofthe p-well 54 as a result of an ESD protection current.

The NMOS transistor may adopt a gate electrode in a finger structure todischarge a large amount of current even though a representativesingular gate electrode is illustrated in FIG. 4A. In this case, then-well 52 vertically extends to connect to the n+ drain 62. In addition,the p+ well pick-up 66 may be formed in the p-well 54 as a guard ringtype that surrounds the ESD protection circuit.

FIG. 4B is an equivalent circuit diagram of an ESD protection deviceaccording to the first embodiment of the present invention.

The ESD protection device operates using a parallel circuit of aparasitic npn bipolar transistor in the NMOS transistor. The n+ source64, the n+ drain 62 and the p-well 54 correspond to an emitter, acollector and a base, respectively, of the first npn bipolar transistorQ₁₁. The n+ source 64, the n-well 52 and the p-well 54 correspond to anemitter, a collector and a base, respectively, of the second npn bipolartransistor Q₁₂.

When an ESD voltage is applied to the n+ drain 62 to break down ajunction among the n+ drain 62, the n-well 5.2 and the p-well 54, thefirst and second npn bipolar transistors Q₁₁ and Q₁₂ are triggered. Avoltage drop by the parasitic resistors R₁ and R₂ of the p-well 54drives the first and second npn bipolar transistors Q₁₁ and Q₁₂ toinstantly discharge the ESD current through a ground terminal. The ESDprotection device discharges the ESD current by operation of a lateralnpn bipolar transistor Q₁₁ and a vertical npn bipolar transistor Q₁₂.The lateral npn bipolar transistor Q₁₁ includes the n+ source 64, the n+drain 62 and the p-well 54. The vertical npn bipolar transistor Q₁₂includes the n+ source 64, the n-well 52 and the p-well 54. Therefore, adischarge current is dispersed to lower a surface current of thesubstrate and suppress Joule heat generated from a surface of thesubstrate.

The impurities of the n-well 52 may raise an impurity concentration ofthe n+ drain 62. Therefore, a junction breakdown voltage between the n+drain 62 and the p-well 54 can be reduced to provide a low triggervoltage for the bipolar transistor. In this case, an impurityconcentration of the n+ drain 62 is highest at a portion where thep-well 54, the n-well 52 and the n+ drain 62 contact one another.Therefore, this portion breaks down first to lower a current density ofthe surface at the region adjacent a gate.

FIG. 5A illustrates a cross-sectional view of an ESD protection deviceaccording to the second embodiment of the present invention.

Referring to FIG. 5A, the ESD protection device similarly includes anNMOS transistor having the n+ drain 62 connected to the n-well 52. Then-well 52 and the p-well 54 are formed in the substrate 50. The p-well54 extends to a surface of the substrate 50. A portion of the n-well 52vertically extends along a sidewall of the p-well 54 to a surface of thesubstrate 50. The device isolation layer 56 is formed in the substrate50 to define an active region. The active region includes the p-wellregion and the n-well region. The gate electrode 58 is formed on theactive region. The gate electrode 58 crosses over the active region and,although not illustrated as doing so, may extend to a surface of thedevice isolation layer 56. The gate electrode 58 divides the activeregion into a first portion of the active at one side of the gateelectrode 58 that includes the p-well region and the n-well region and asecond portion of the active region to the other side of the gateelectrode 58 that includes only the p-well region. The n+ source 64 andthe n+ drain 62 are formed in the active regions to either side of thegate electrode 58. The gate electrode 58, the n+ source 64 and the n+drain 62 compose an NMOS transistor. In the second embodiment of thepresent invention, a dielectric layer (not shown in FIG. 5A; 224 of FIG.11), which may be thick, is interposed between the gate electrode 58 andthe active region. The n+ source 64 is formed in the p-well 54, and then+ drain 62 is formed to overlap the p-well 54 and the n-well 52.Therefore, a drain of the NMOS transistor in the ESD protection deviceincludes a drain 62 overlapping the p-well 54 and the n-well 62 tocontact the n-well 62. The n+ drain 62 may have an impurityconcentration higher than that of the n+ source 64 due to an influenceof the n-well 52.

A p+ well pick-up 66 doped with impurities is formed in the p-well 54.The p+ well pick-up 66 may be separated from the NMOS transistor by thedevice isolation layer 56. The n+ drain 62 is connected to a circuitterminal 60 of the integrated circuit. In the second embodiment of thepresent invention, the n+ source 64 and the p+ well pick-up 66 areconnected to a ground terminal, and the gate electrode 58 and the n+drain 62 are connected to the circuit terminal 60. A threshold voltageof the NMOS transistor may be high to maintain the NMOS transistor ofthe ESD protection device at turn-off at a steady state. Therefore, theinsulating layer is interposed between the gate electrode 58 and theactive region. The gate electrode 58 may be an extended portion of aninterconnection, which will be described below, connected to the n+drain 62. In this case, the interlayer dielectric layer may correspondto a gate insulation layer.

Although a representative singular gate electrode is illustrated in FIG.5A, the NMOS transistor may adopt a gate electrode in a finger structureto discharge a large amount of current. In this case, the n-well 52vertically extends to connect to the n+ drain 62. In addition, the p+well pick-up 66 may be formed in the p-well 54 as a guard ring typesurrounding the ESD protection circuit.

FIG. 5B is an equivalent circuit diagram of the ESD protection deviceaccording to the second embodiment of the present invention.

Referring to FIG. 5B, the ESD protection device operates using an NMOStransistor T₁₁ and parasitic npn bipolar transistors Q₂₁ and Q₂₂ in theNMOS transistor T₁₁. The n+ source 64, the n+ drain 62 and the p-well 54correspond to an emitter, a collector and a base, respectively, of thefirst npn bipolar transistor Q₂₁. The n+ source 64, the n-well 52 andthe p-well 54 correspond to an emitter, a collector and a base,respectively, of the second npn bipolar transistor Q₂₂.

When a junction among the n+ drain 62, the n-well 52 and the p-well 54breaks down due to application of an ESD voltage to the n+ drain 62, thefirst and second npn bipolar transistors Q₂₁ and Q₂₂ are triggered. Thefirst and second npn bipolar transistors Q₂₁ and Q₂₂ are driven by avoltage drop due to parasitic resistances R₂₁ and R₂₂ of the p-well 54,such that an ESD current is instantly discharged to a ground terminal.The ESD protection device discharges ESD current by operation of alateral npn bipolar transistor Q₂₁, a vertical npn bipolar transistorQ₂₂ and the NMOS transistor T₁₁. The lateral npn bipolar transistor Q₂₁includes the n+ source 64, the n+ drain 62 and the p-well 54. Thevertical npn bipolar transistor Q₂₂ includes the n+ source 64, then-well 52 and the p-well 54. That is, the transistors are triggered atthe lowest one of a junction breakdown voltage between the n+ drain 62and the p-well 54, a junction breakdown voltage between the n-well 52and the p-well 54, and a threshold voltage of the NMOS transistor T₁₁,thereby instantly discharging the ESD current.

FIGS. 6 through 8 illustrate cross-sectional views of stages in a methodof forming the ESD protection device according to the first embodimentof the present invention.

Referring to FIG. 6, a deep n-well 102 is formed by implantingimpurities in a substrate 100. A vertical n-well 104 is formed byimplanting impurities in the substrate 100. The deep n-well 102 isseparated a predetermined distance apart from a surface of thesubstrate. The vertical n-well 104 is connected to the deep n-well 102and extends vertically to the surface of the substrate 100.

A CMOS integrated circuit may have various well structures. For example,the integrated circuit may include a p-well where an NMOS transistor isformed, an n-well where a PMOS transistor is formed and a pocket p-wellfor a well biasing and a well isolation, etc. Therefore, the deep n-well102 and the vertical n-well 104 may be formed without additionalprocesses by changing an existing layout. A device isolation layer 108may be formed before forming the wells. A first active region 110 a is aregion where the NMOS transistor of the ESD protection device is to beformed. A second active region 110 b is a region where a well pick-up isto be formed. In an alternative configuration, the second active region110 b may be omitted and the well pick-up may be formed in the firstactive region 110 a. A surface of the first active region 110 a includesa p-well region where a p-well 106 is formed and an n-well region wherethe vertical n-well 104 is formed.

Referring to FIG. 7, a gate electrode 112 is formed on the first activeregion 110 a. A gate insulating layer 111 is interposed between the gateelectrode 112 and the first active region 110 a. The gate electrode 112crosses over the first active region 110 a extends over the deviceisolation layer 108. The gate electrode 112 divides the first activeregion 11 Oa into two portions. The first active region 110 a at oneside of the gate electrode 112 is a p-well region, and the first activeregion 110 a at another side of the gate electrode 112 includes thep-well region and the n-well region. An n+ source 116 and an n+ drain114 are formed to either side of the gate electrode 112 by implantingimpurities in the first active region 110 a. The n+ source 116 is formedin the p-well region, and the n+ drain 1 14 is formed to overlap thep-well region and the n-well region. Therefore, the n+ drain 114 isconnected to the vertical n-well 104. Impurities are implanted in thep-well region to form a p+ well pick-up 118. The p+ well pick-up 118 isformed in the second active region 110 b, as described above, the secondactive region 110 b is not formed, the p+ well pick-up 118 may be formedto have a guard ring shape surrounding the ESD protection device. Byadopting a guard ring structure, an ESD current flowing through thep-well 106 is concentrated in one direction, such that an increase ofthe current density may be prevented.

The p+ well pick-up 118, the n+ source 116 and the n+ drain 114 may beformed during a formation of a diffusion layer in an internal circuit.Therefore, a formation order may be varied according to an order offorming the internal circuit.

Referring to FIG. 8, an interlayer dielectric layer 124 is formed on anentire surface of the substrate. The interlayer dielectric layer 124 ispatterned to form contact holes exposing each of the p+ well pick-up118, the n+ source 116, the n+ drain 114 and the gate electrode 112.Although not illustrated in FIG. 8, the contact hole exposing the gateelectrode 112 may be placed over the device isolation layer 108. Thatis, the contact hole exposing the gate electrode 112 may be formed overthe portion of gate electrode 112 extending over the device isolationlayer 108.

An interconnection, including a first interconnection 126 and a secondinterconnection 128, is then formed on the interlayer dielectric layer124. The first interconnection 126 extends through one of the contactholes to contact the n+ source 116. The second interconnection 128extends through one of the contact holes to contact the n+ drain 114.The first interconnection 126 may extend through another of the contactholes to contact the gate electrode 112. In the drawing, the firstinterconnection 126 and the second interconnection 128 are illustratedas a single layer, but the first and second interconnection 126 and 128may have a multi-layered structure. That is, local interconnections maybe formed on the interlayer dielectric layer 124 and then anotherinterlayer dielectric layer may be further formed on the localinterconnections, such that global interconnections may be formed toconnect the local interconnections. The local interconnections and theglobal interconnections may be formed using conventional multipleinterconnections technology.

A silicide layer 122 may be further formed on surfaces of the n+ source116, the n+ drain 114 and the p+ well pick-up 118 before forming theinterlayer dielectric layer 124. An additional silicide layer (notshown) may be formed on a top surface of the gate electrode 112. Thesilicide layer 122 may be formed by applying a conventional self-alignedsilicidation process. A spacer pattern 120 may prevent a short of thesilicide layer 122 and the gate electrode 112 and also form a ballastresistance between the silicide layer and the junction. Even if thesilicide layer 122 is not formed, the spacer pattern 120 may becollectively formed in an integrated circuit device to junction engineerthe internal circuit.

Although not illustrated in the drawings, the first interconnection 126is connected to a ground terminal, and the second interconnection 128 isconnected to a circuit terminal analogous to that shown in FIG. 4A.

FIGS. 9 through 11 illustrate cross-sectional views of stages in amethod of fabricating an ESD protection device according to the secondembodiment of the present invention.

Referring to FIG. 9, a deep n-well 202 is formed by implantingimpurities into a substrate 200. A vertical n-well 204 is formed byimplanting impurities in the substrate. The deep n-well 202 is separateda predetermined distance apart from a surface of the substrate 200. Thevertical n-well 204 is connected to the deep n-well 202 and verticallyextends to a surface of the substrate 200. The deep n-well 202 and thevertical n-well 204 may be formed without an additional process bychanging a conventional layout.

A p-well 206 is formed by implanting impurities in the substrate 200 onthe deep n-well 202. A device isolation layer 208 is formed in thesubstrate 200 including the wells to define the first active region 210a and the second active region 210 b. The device isolation layer 208 maybe formed before forming the wells. The second active region 210 b is aregion where the well pick-up is to be formed. If the well pick-up isformed in the first active region 210 a, the second active region 201 bmay not be formed. A surface of the first active region 210 a includes ap-well region where the p-well 206 is formed, and an n-well region wherethe vertical n-well 204 is formed.

A dummy gate pattern 212 is formed on the active region 210 a. The dummygate pattern 212 crosses over the first active region 210 a and aportion thereof extends over the device isolation layer 208. A portionof the first active region 210 a at one side of the dummy gate pattern212 is a p-well region, and another portion of the first active region210 a at another side of the dummy gate pattern 212 includes the p-wellregion and the n-well region. Impurities are implanted in the firstactive region 210 a such that an n+ source 216 and an n+ drain 214 areformed to either side of the dummy gate pattern 212. The n+ source 216is formed in the p-well region, and the n+ drain 214 is formedoverlapping the p-well region and the n-well region. Therefore, the n+drain 214 is connected to the vertical n-well 204. Impurities areimplanted in the p-well region to form a p+ well pick-up 218. The p+well pick-up 218 is formed in the second active region 210 b. If thesecond active region 210 b is not formed, as described above, the p+well pick-up 218 may be formed in the first active region 210 a. The p+well pick-up 218 may be formed to have a guard ring shape surroundingthe ESD protection device. By adopting the guard ring structure, ESDcurrent flowing through the p-well 206 is concentrated in one directionto prevent the current density from increasing.

The p+ well pick-up 218, the n+ source 216 and the n+ drain 214 may beformed when an impurity diffusion layer of the internal circuit isformed. Thus, an order of forming those elements may be varied accordingto an order of forming an internal circuit.

Referring to FIG. 10, an interlayer dielectric layer 224 is formed on anentire surface of the internal circuit. The interlayer dielectric layer224 is patterned to form contract holes 225 exposing each of the p+ wellpick-up 218, the n+ source 216 and the n+ drain 214. The dummy gatepattern 212 may be removed before forming the interlayer dielectriclayer 224. If the dummy gate pattern 212 is an insulating layer, aninterlayer dielectric layer 224 may be formed on the dummy gate pattern212 and then planarized.

Before the interlayer dielectric layer 224 is formed, a silicide layer222 may be further formed on a surface of the n+ source 216, the n+drain 214 and the p+ well pick-up 218. In this case, a silicide layermay not be formed at the region between the n+ source 216 and the n+drain 214 because of the dummy gate pattern 212. The dummy gate pattern212 may then be removed after the silicide layer 222 is removed.

Referring to FIG. 11, an interconnection, which includes a firstinterconnection 226 and a second interconnection 228, is formed on theinterlayer dielectric layer 224. The first interconnection 226 extendsthrough the contact holes 225 to connect to the p+ well 218 and the n+source 216. The second interconnection 228 extends through one of thecontact holes 225 to connect to the n+ drain 214. The secondinterconnection 228 may extend over the region between the n+ source 216and the n+ drain 214. In this case, one sidewall of the secondinterconnection 228 may overlap the n+ source 216. If a voltage over apredetermined level is applied to the second interconnection 228, achannel may be formed at the first active region 210 a between the n+source 216 and the n+ drain 214. That is, an extended portion G of thesecond interconnection 228, the n+ source 216 and the n+ drain 214 maycompose a MOS transistor. In this case, the interlayer dielectric layer224 between the extended portion G and the first active region 210 a maycorrespond to a gate interlayer dielectric layer of the MOS transistor.In FIG. 11, the first and second interconnections 226 and 228 areillustrated as a single layer, but each of the first and secondinterconnections 226 and 228 may be formed to have a multi-layeredstructure. That is, local interconnections may be formed on theinterlayer dielectric layer 224 and then other interlayer dielectriclayers may be additionally formed on the local interconnections, therebyforming global interconnections for connecting the localinterconnections. The local interconnections and the globalinterconnections may be formed using a conventional multipleinterconnections technology.

Although not illustrated in the drawings, the first interconnection 226is connected to a ground terminal, and the second interconnection 228 isconnected to a circuit terminal analogous to that shown in FIG. 5A. Whenan ESD voltage is applied to the second interconnection 228, the ESDprotection device operates. If the ESD voltage is higher than apredetermined level, the extended portion G of the secondinterconnection 228 may form a channel formed between the n+ source 216and the n+ drain 214 to discharge the ESD current to the ground terminalthrough the n+ source 216.

According to the present invention, an ESD current is discharged througha ground terminal by operation of both a lateral npn bipolar transistorand a vertical npn bipolar transistor, such that a current density of aweak substrate surface can be reduced. Since the current is dischargedaccording to a bulk path of substrate spaced apart from the substratesurface, Joule heating generating from the substrate surface can besuppressed. In addition, an n-well and an n+ drain are connectedtogether such that an impurity concentration of the n+ drain isincreased by the impurities of the n-well. If a trigger voltage is low,ESD is effectively prevented and a stress of the ESD protection devicecan be reduced.

Moreover, the n-well connected to the drain may be formed while formingthe well structure of the internal circuit only by changing a typicallayout. Therefore, the existing process can be applied as it is becausean additional process is not required. In addition, the presentinvention changes a well structure without increasing lateraldimensions, such that the ESD protection device can have improvedintolerance without an increased area.

Exemplary embodiments of the present invention have been disclosedherein and, although specific terms are employed, they are used and areto be interpreted in a generic and descriptive sense only and not forpurpose of limitation. Accordingly, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentinvention as set forth in the following claims.

1. An electrostatic discharge protection device, comprising: asubstrate; an n-well formed in the substrate; a p-well formed on then-well; an NMOS transistor formed on the p-well, the NMOS transistorincluding a gate electrode, an n+ source and an n+ drain; and a groundedp+ well pick-up formed in the p-well, wherein the n-well is connected tothe n+ drain of the NMOS transistor and the n+ source is grounded. 2.The device as claimed in claim 1, wherein the gate electrode isgrounded.
 3. The device as claimed in claim 1, wherein the gateelectrode is electrically connected to the n+ drain.
 4. The device asclaimed in claim 1, wherein an impurity concentration of the n+ drain ishigher than that of the n+ source.
 5. The device as claimed in claim 1,wherein the n-well extends vertically under the n+ drain and contactsthe n+ drain.
 6. The device as claimed in claim 1, wherein the n-wellextends vertically to form a junction with the p-well, and wherein ajunction of the n-well and the p-well overlaps the n+ drain.
 7. Anelectrostatic discharge protection device, comprising: a p-well regionformed in a substrate; an NMOS transistor formed on the p-well region,the NMOS transistor including a gate electrode and an n+ source that areelectrically connected to a ground terminal and an n+ drain electricallyconnected to a circuit terminal; a p+ well pick-up formed in the p-wellregion, electrically connected to the ground terminal; and an n-wellformed under the p-well region, wherein the n-well extends vertically tocontact the n+ drain of the NMOS transistor.
 8. The device as claimed inclaim 7, further comprising an interconnection connected to the groundterminal, wherein the n+ source, the gate electrode and the p+ wellpick-up are connected to the interconnection in parallel.
 9. The deviceas claimed in claim 7, wherein an impurity concentration of the n+ drainis higher than that of the n+ source.
 10. An electrostatic dischargeprotection device connected to a circuit terminal and a ground terminal,comprising: a p-well region formed in a substrate; an NMOS transistorformed on the p-well region, the NMOS transistor including a gateelectrode electrically connected to the circuit terminal, an n+ sourceelectrically connected to the ground terminal and an n+ drainelectrically connected to the circuit terminal; a p+ well pick-up formedin the p-well region to be electrically connected to the groundterminal; and an n-well formed under the p-well region, wherein then-well extends vertically to contact the n+ drain of the NMOStransistor.
 11. The device as claimed in claim 10, further comprising afirst interconnection connected to the ground terminal, wherein the n+source and the p+ well pick-up are connected to the firstinterconnection in parallel.
 12. The device as claimed in claim 10,further comprising a second interconnection for connecting the circuitterminal and the n+ drain, wherein the gate electrode is an extendedportion of the second interconnection.
 13. The device as claimed inclaim 10, wherein an impurity concentration of the n+ drain is higherthan that of the n+ source.
 14. A method of fabricating theelectrostatic discharge protection device, comprising: forming a p-wellregion at an upper portion of a substrate and an n-well region under thep-well region, wherein the n-well region extends vertically along asidewall of the p-well region to define a junction between the p-wellregion and the n-well region at a surface of the substrate; forming ann+ source and an n+ drain separated from each other by implantingimpurities in the p-well region, wherein the n+ drain is formed tooverlap the junction of the p-well region and the n-well region; forminga p+ well pick-up by implanting impurities in the p-well region; andforming an interconnection connected to each of the p+ well pick-up, then+ source and the n+ drain, wherein the p+ well pick-up and the n+source are connected to a ground terminal, and the n+ drain is connectedto a circuit terminal.
 15. The method as claimed in claim 14, furthercomprising forming a device isolation layer in the substrate to definean active region, before forming the n-well region and the p-wellregion, wherein the active region includes the n-well region and thep-well region, and the n+ source, the p+ well pick-up and the n+ drainare formed in the active region.
 16. The method as claimed in claim 14,further comprising forming a device isolation layer in the substrate todefine an active region, after forming the n-well region and the p-wellregion, wherein the active region includes the n-well region and thep-well region, and the n+ source, the p+ well pick up and the n+ drainare formed in the active region.
 17. The method as claimed in claim 14,wherein an interconnection connected to the n+ drain extends over aregion between the n+ source and the n+ drain, such that an edge of theinterconnection overlaps the n+ source.
 18. A method of fabricating anelectrostatic discharge protection device connected to a circuitterminal and a ground terminal, comprising: forming a p-well region atan upper portion of a substrate and an n-well region under the p-wellregion, wherein the n-well region extends vertically along a sidewall ofthe p-well region to define a junction of the p-well region and then-well region at a surface of the substrate; forming a gate electrode onthe p-well region; implanting impurities in the substrate at either sideof the gate electrode to form an n+ source and an n+ drain, wherein then+ drain is formed to overlap a junction between the p-well region andthe n-well region; implanting impurities in the p-well region to form ap+ well pick-up; and forming an interconnection connecting each of thep+ well pick-up, the gate electrode, the n+ source and the n+ drain,wherein the p+ well pick-up and the n+ source are connected to theground terminal, and the n+ drain is connected to the circuit terminal.19. The method as claimed in claim 18, further comprising forming adevice isolation layer in the substrate to define an active region,before forming the n-well region and the p-well region, wherein theactive region includes the n-well region and the p-well region, the gateelectrode crosses over the p-well region in the active region, andwherein the active region at one side of the gate electrode includes thep-well region and the active region at the other side of the gateelectrode includes the p-well region and the n-well region.
 20. Themethod as claimed in claim 18, further comprising forming a deviceisolation layer in the substrate to define an active region, afterforming the n-well region and the p-well region, wherein the activeregion includes the n-well region and the p-well region, and wherein thegate electrode crosses over the p-well region in the active region, andthe active region at one side of the gate electrode is the p-well regionand the active region at the other side includes the p-well region andthe n-well region.
 21. The method as claimed in claim 18, wherein thegate electrode is connected to a ground terminal.